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W99802G Data Sheet MOBILE MULTIMEDIA PROCESSOR
Table of Contents1. 2. 3. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 PIN DESCRIPTION..................................................................................................................... 7 3.1 W99802G Pin Definition ................................................................................................. 7
3.1.1 3.1.2 Pin Type Definition .....................................................................................................7 Pin List........................................................................................................................7
3.2 4. 5.
W99802G Pin Assignment (Bottom View).................................................................... 15
W99802G BLOCK DIAGRAM................................................................................................... 16 ELECTRICAL CHARACTERISTICS......................................................................................... 17 5.1 5.2 5.3 Digital Absolute Maximum Ratings............................................................................... 17 Digital DC Characteristics............................................................................................. 17 Digital AC Characteristics ............................................................................................. 18
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 Reset AC Characteristics..........................................................................................18 Clock Input Characteristics .......................................................................................18 Video Input AC Characteristics.................................................................................19 Host Interface: Memory Bus AC Characteristic ........................................................20 LCD Interface AC Characteristics.............................................................................21 SD/MMC Host Interface AC Characteristics .............................................................22 NAND Flash Memory Interface AC Characteristics ..................................................23 Audio I2S Interface AC Characteristics.....................................................................24 Host Universal Synchronous Serial Interface AC Characteristics .............................25 USB Transceiver AC Characteristics........................................................................26 Recommend Operation Conditions...........................................................................28 Electrical Characteristics ..........................................................................................28
5.4
Audio Interface (ADC) Characteristics.......................................................................... 28
5.4.1 5.4.2
6. 7. 8.
PACKAGE DIMENSION ........................................................................................................... 29 W99802G APPLICATION DIAGRAM ....................................................................................... 30 REVISION HISTORY ................................................................................................................ 31
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
1. GENERAL DESCRIPTION
W99802G is a highly integrated, low-power and high performance MPEG-4 audio/video chip with embedded memory for multimedia cellular phones. It contains a 32-bit ARM CPU, Sensor ISP, JPEG image codec, MPEG-4 video codec, Audio engine, 2-D graphics engine, video processing engine, display controller, USB 1.1 device controller, and flash memory card interface. W99802G supports 8-bit YCbCr or 10-bit raw data RGB CMOS / CCD sensor interface and provides advanced AEC / AWB / AFC algorithm to deliver professional photo image quality. The supported image resolution can be up to 3M pixels. The JPEG image codec is compliant with ISO/IEC 10918-1 baseline standard and JFIF format. It is capable of encoding or decoding 30fps JPEG pictures at VGA resolution. The MPEG-4 video codec is compliant with ISO/IEC 14496-2 Visual standard Simple Profile Level 3. It can also support H.263 short header mode for the implementation of 3GP movie. The video codec supports smart bit rate control and performs up to 30fps VGA simultaneous encode and decode for video conferencing applications. The audio engine integrates a single channel 16-bit ADC, as well as audio control interface for external audio codec or melody chip. W99802G can provide voice recorder and high quality MP3 and AAC music playback. The 2-D graphics engine is used for MMI and JAVA acceleration. The video processing engine is used for the image / video data processing. It can provide versatile functions for image / video capture and playback such as sticker, rotation, color effects, etc. The display controller can support dual LCM display and bypass mode. The supported LCM can be up to 262K colors. The USB device controller is compliant with USB1.1 specification and can support configurable pipes for rich USB functions such as Mass storage, PC camera, Virtual COM port and PictBridge. The flash memory card interface can support embedded NAND type flash and SD / mini-SD / MMC / RS-MMC / T-Flash for storing multimedia data.The file system is FAT compatible and can be accessed by host through host interface. The internal 32-bit ARM CPU handles audio/video synchronization, file system and all multimedia functions such as still camera, video camcorder, MP3 player and voice recorder according to the highlevel commands from host. The host driver programmer can control W99802G without knowing its register programming to shorten the development cycle.
2. FEATURES
CPU * * * * Built-in 32-bit ARM CPU with I-cache and D-cache. Programmable with CPU operating frequency from 200KHz to 166MHz. Program code can be downloaded into program buffer through Host Interface or JTAG port. Integrate JTAG port to support real time, non-stop ICE function for system development and debug.
Sensor Interface and ISP * Support up to 3M pixels CMOS / CCD image sensor.
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W99802G
* * * * * Support 8-bit CCIR-656 YCbCr or 10-bit raw RGB Bayer input format. Support both master mode and slave mode sensors. Support universal serial interface to program CMOS / CCD image sensor. Support 30fps real-time preview. Support sensor ISP for color image processing: - Black Level Clamping - Missing Color Interpolation - Auto Exposure Control (AEC) - Auto White Balance Control (AWB) - Auto Focus Control (AFC) - Bad Pixel Concealment - Flash Light Control - Lens Shading Compensation - False Color Suppression - Edge Enhancement - Color Correction - Gamma Correction - Contrast Stretching / Hue / Saturation Adjustment * * * * * * Support complete software utilities for sensor module calibration.
Video Processing Engine Support hardware image sticker function for both preview and compression data. Support real-time hardware flip / mirror / rotation (90, 180 and 270 degree) function. Support special image color effect functions such as B&W, Negative, Sepia, Oil, Emboss, Binary, etc. Support linear scaling down from 1 ~ X/256 with 2D filter for better image quality. Support YUV-to-RGB and RGB-to-YUV Color Format Conversion and Data Format Transformation for video display and image editing. Support MPEG4 Simple Profile Level 3 compression tools and compliant with ISO/IEC 144962 Visual Standard. Support I-VOP and P-VOP. Support motion estimation with 16x16 search range and half pixel resolution. Support AC/DC prediction, 4 motion vectors per macro block, unrestricted motion compensation. Support RVLC and Data Partitioning for error resilience. Support Short Header Mode (H.263 baseline). Support real-time 30fps video compression/decompression up to VGA resolution. Support smart bit rate control and simultaneous encode/decode for video conferencing application. Publication Release Date: Mar. 3, 2006 Revision A0
MPEG-4 Video Codec * * * * * * * *
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W99802G
JPEG Image Codec * * * * * * * * * * * Compliant with ISO/IEC 10918-1 internal JPEG standard. Support resolution up to 3M pixels and capable of encoding or decoding 30fps real-time VGA JPEG. Support YUV 4:2:2 and 4:2:0 formats encode. Support YUV 4:4:4, 4:2:2 and 4:2:0 formats decode. Support programmable quantization table. Support programmable Huffman table decoding. Capable of decoding JPEG image with specified rectangle to a specified size. Support resolution scaling up and 1x ~ 8x linear digital zoom. Support JPEG resizing and trimming. Support thumbnail image. Support JPEG Exchangeable Image File (EXIF) format.
Audio Engine * Support I2S codec interface to connect with external audio codec. * * * * Support audio control interface for external melody chip Integrate a 16-bit ADC for microphone analog input Support MP3 / AMR-WB decoder. Support AAC-LC / AMR-NB / ADPCM codec.
2-D Graphics Engine * Support 8/16/32-bpp graphics modes. * Support 5 Bit Block Transfer (BLT) function with ROP function. - Write BitBLT - Read BitBLT - Copy BitBLT - Pattern Fill BitBLT - Solid Fill BitBLT Hardware Clipper. Tile BLT. Mono-to-Color Expansion for text output acceleration. Transparency Control (Sprites). Image Blending (Semi-Transparency). Bit Plane Mask. Programmable 2D filter functions for special color effects. Support Bresenham Line and Frame Drawing.
* * * * * * * *
Display Controller * Support 8/12/16/18-bit RGB data output interface to connect with 80/68 series MPU type LCM module. * * Support LCM resolution up to 240 320. Support dual LCM control for MPU interfaced LCM. -4-
W99802G
* * * * * * * Support LCM bypass mode that allows the host to access LCM directly while W99802G is in suspend mode. Support RGB444 (4K colors), RGB565 (65K colors) and RGB666 (262K colors) color formats for display output. Support 8/16/32-bit graphics mode OSD. Support graphics / video overlay using color key and alpha blending control. Support playback pan / tilt / zoom. Support CCIR-656 8-bit YUV output for external TV encoder. Support picture-in-picture display for video conferencing applications.
USB Device Controller * Compliant with USB 1.1 specification. * * * * * Support four USB pipes including one control pipe and 3 configurable pipes for rich USB functions. Support USB Mass Storage. Support USB PC Camera (DirectShow). Support USB Virtual COM Port with modem capability. Support USB PictBridge.
Memory Card Interface * Support NAND Type flash. * Support SD, mini-SD, MMC, RS-MMC,and T-Flash. Host Bus Interface * Support 8/9/16/18-bit parallel slave interface to connect with 80 or 68 series host MPU. * * * * * * Support bypass mode to allow the host to access the LCM and melody chip directly. Support DMA data transfer between host MPU and W99802G. Allow host to access W99802G memory buffer and control registers.
Peripheral Support Support two Timers and one programmable 24-bit Watch-Dog timer. Supports universal synchronous serial interface for connecting with synchronous serial device. Support GPIOs for system control.
J2ME MIDP 2.0 Graphics / Game native layer acceleration Multimedia File Format Support * * * * * 3GP (H.263+AMR-NB) MP4 (MP4+AAC-LC) AVI ASF
Flash File System Support Support FAT12/16/32 Publication Release Date: Mar. 3, 2006 Revision A0
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W99802G
* * * Support long filename.
Power Supply Host Interface: 1.8V - 3.3V I/O Power Supply: - General Digital I/O: - USB Transceiver: - Audio ADC: 2.5V - 3.3V 3.0V - 3.3V 2.5V - 3.3V
Package: LFBGA 184-Balls package (10mm x 10mm), Lead-free.
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W99802G
3. PIN DESCRIPTION
3.1 W99802G Pin Definition
The following signal types are used in these descriptions.
3.1.1
Pin Type Definition
TYPE DESCRIPTION
I IS B BU BD O A P G #
Input pin Input pin with Schmitt trigger Bi-directional input/output pin Bi-directional input/output pin with internal pull-up Bi-directional input/output pin with internal pull-down Output pin Analog input/output pin Power supply pin Ground pin Active low
3.1.2
Pin List
USB Interface
PIN NAME PIN NUMBER TYPE DESCRIPTION
DP DM USBVDD USBVSS
B1 D2 D18 E7
A A P G
USB DP (D+) Signal USB DM (D-) Signal USB Power Supply +3.3V 0.3V. USB Ground.
Sensor or Video Input Interface
PIN NAME PIN NUMBER TYPE DESCRIPTION
SVID[1:0] / GPIOA[1:0] SVID[9:2] SPCLK SVS SHS SCLK
J6, N1 K18, L6, G18, R1, J18, N2, P1, K6 P2 R2 N18 L5
BD ID ID BD BD O
Sensor Data Input [1:0] GPIO Function : GPIOA[1:0] Sensor Data Input [9:2] Clock Input from Sensor for Pixel Data Vertical Sync. Horizontal Sync. Clock Output to Sensor
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
Sensor or Video Input Interface, continued
PIN NAME
PIN NUMBER
TYPE
DESCRIPTION
SCK / GPIOA[2] SDI/SDA / GPIOA[3] SDO/SDE / GPIOA[4] Audio Digital Interface
PIN NAME
T1 L13 L14
BU BU BU
Serial Interface Clock GPIO Function: GPIOA[2] Serial Data Input/ Serial Data Acknowledge GPIO Function: GPIOA[3] Serial Interface Data Output / Serial Data Enable GPIO Function: GPIOA[4]
PIN NUMBER
TYPE
DESCRIPTION
ASCLK / GPIOA[8] ADO / GPIOA[9] AWS / GPIOA[10] ABCLK / GPIOA[11] ADI / GPIOA[12] ARST# / GPIOA[13] Audio Analog Interface
PIN NAME
F2 M18 F1 G5 F8 E1
BU BU BU BD BD BD
Audio Interface: Audio System Clock GPIO Function: GPIOA[8] Audio Interface: I2S=> Audio Data Output GPIO Function: GPIOA[9] Audio Interface: I2S=> Audio Word Select GPIO Function: GPIOA[10] Audio Interface: I2S=> Audio Bit Clock Output GPIO Function: GPIOA[11] Audio Interface: I2S=> Audio Data Input GPIO Function: GPIOA[12] Audio Interface: Audio Reset GPIO Function: GPIOA[13]
PIN NUMBER
TYPE
DESCRIPTION
CAD1 MIC_IN MIC_BIAS VREFC ADO_AVDD ADO_AVSS ADO_DVDD ADO_DVSS
B2 A2 B17 B18 A17 B15 J13 C1
A A A A P G P G
Decoupling for ADC Audio (Microphone) Input Microphone Bias ADC Reference Voltage Audio ADC Analog Power Supply +3.3V Audio ADC Analog Ground Audio Digital Power Supply Audio Digital Ground
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W99802G
JTAG Interface Pins
PIN NAME PIN NUMBER TYPE DESCRIPTION
TCK TMS TDI TDO TRST# UART Interface Pins
PIN NAME
U12 V16 V12 U11 V11
ID IU IU O IU
JTAG Test Clock JTAG Test Mode Select JTAG Test Data in JTAG Test Data out JTAG Reset
PIN NUMBER
TYPE
DESCRIPTION
RTS# / GPIOA[16] DTR# / GPIOA[17] SOUT / GPIOA[18] CTS# / GPIOA[19] DSR# / GPIOA[20] RLSD# / GPIOA[21] RI# / GPIOA[22] SIN / GPIOA[23] SOUT2 / GPIOA[24] SIN2 / GPIOA[25]
K14 N5 K17 U2 U5 U4 L18 M14 V2 U1
BD BD BD BD BD BD BD BD BD BD
Request To Send / GPIO Function: GPIOA[16] Data Terminal Ready GPIO Function: GPIOA[17] Serial Data Output (TXD) GPIO Function: GPIOA[18] Clear To Send GPIO Function: GPIOA[19] Data Set Ready GPIO Function: GPIOA[20] Receive Line Signal Detect GPIO Function: GPIOA[21] Ring Indicator GPIO Function: GPIOA[22] Serial Data Input (RXD) GPIO Function: GPIOA[23] Serial Data Output -2 (High Speed TXD) GPIO Function: GPIOA[24] Serial Data Input - 2 (High Speed RXD) GPIO Function: GPIOA[25]
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
LCM Interface
PIN NAME PIN NUMBER TYPE DESCRIPTION
LCLK / LA0 LCLKO / LCS0# LCS1# / GPIOB[17] LWR# / LR/W#/ LHSYNC LRD# / LE / LVSYNC LDAT [7:0] LDAT [15:8] GPIOB[7:0] LDAT [17:16] / GPIOB[9:8] LCS2# GPIOB[16]
H13 H5 G1
BD
Clock Input for output Data to TV encoder LCM Interface (O): Address-0, R/S# (CMD/DAT#) Clock for Digital Display Data Output LCM Interface : LCD Chip Select-0 LCM Interface : LCD Chip Select-1 GPIO Function : GPIOB[17] LCM 80-series interface: Write Enable, Active Low LCM 68-series interface: "1" => Read, "0"=> Write Horizontal Sync to TV encoder LCM 80-series interface: Read Enable, Active Low
O BU
H1
O
G17 L1, H17, L2, J17, M1, H6, M2, H18 H2, J5, H14, K5, K1, J2, J14, K2 G2,J1 G14
O
LCM 68-series interface: Data Enable, Active High Vertical Sync to TV encoder
BU
LCM Data Bus / TV-encoder Data Bus Bit-7_0 LCM Data Bus Bit-15_8 GPIO Function : GPIOB[7:0] LCM Data Bus Bit-17_16 GPIO Function : GPIOB[9:8] MCU Interface : LCD Chip Select 2 GPIO Function : GPIOB[16]
BU
BU BU
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W99802G
Memory Bus Interface
PIN NAME PIN NUMBER TYPE DESCRIPTION
MSCE# MSA3 MSWR# / MSR/W# MSRD# / MSE MSA[2:0] MSD[7:0] / MSD[15:8] / GPIOB[31:24] MSD[16] / GPIOB[18] MSD[17] GPIOB[19]
E8 B6 A5 E10 F17, A4, B14 F11, B9, F10, A8, E17, A7, E11, B7 F14, A11, B11, A10, D17, B10, E12, A9 B8 A6
BU BU BU BU BD BD
Memory Slave (I) : Chip Enable Signal Memory Slave (I) : Address - 3 Memory Slave 80 (I): Write Enable Signal Memory Slave 68 (I): Read/Write Control Memory Slave 80 (I): Read Enable Signal Memory Slave 68 (I): Data Enable Memory Slave (I): Address MSA[2:0] Memory Slave (I): Data Bus Bit-7_0 Memory Slave (I): Data Bus Bit-15_8 GPIO Function: GPIOB[31:24] Memory Slave (I): Data Bus Bit-16 GPIO Function : GPIOB[18] Memory Slave (I) : Data Bus Bit-17 GPIO Function : GPIOB[19]
BD
BD BD
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
NAND / SD / MMC Memory Card Interface
PIN NAME PIN NUMBER TYPE DESCRIPTION
SCS0# / GPIOS[0] SCS1# / SD_CLK / GPIOS[1] / MMC_CLK SALE / GPIOS[2] SCLE / GPIOS[3] SWE# / GPIOS[4] SRE# / GPIOS[5] SRB# / GPIOS[6] SWP# / GPIOS[7] SD[0] / SD_DAT0 / GPIOS[8]/ MMC_DO SD[2:1] / SD_DAT[2:1] / GPIOS[10:9] SD[3]/ SD_DAT[3] / GPIOS[11]/ MMC_CS# SD[4] SD_CMD / GPIOS[12]/ MMC_DI SD[7:5] / GPIOS[15:13]
P13
BU
NAND Flash Interface =>(O): Chip-0 Enable GPIO Function: GPIOS[0] NAND Flash Interface =>(O): Chip-1 Enable SD : Clock GPIO Function: GPIOS[1] MMC : Clock NAND Flash Interface => (O): Address Latch Enable GPIO Function: GPIOS[2] NAND Flash Interface => (O): Command Latch Enable GPIO Function: GPIOS[3] NAND Flash Interface => (O): Write Enable GPIO Function: GPIOS[4] NAND Flash Interface => (O): Read Enable GPIO Function: GPIOS[5] NAND Flash Interface => (I): Ready/Busy Signal GPIO Function: GPIOS[6] NAND Flash Interface => (O): Write Protect GPIO Function: GPIOS[7] NAND Flash Interface => (I/O): Data Bus Bit-0 SD : Data-0 GPIO Function: GPIOS[8] MMC : Data-Out NAND Flash Interface => (I/O): Data Bus Bit-2_1 SD : Data-2:1 GPIO Function: GPIOS[9] NAND Flash Interface => (I/O): Data Bus Bit-3 SD : Data-3 GPIO Function: GPIOS[10] MMC : Chip Select NAND (I/O): Data Bus Bit-4 SD : Command GPIO Function: GPIOS[11] MMC : Data-In NAND Flash Interface => (I/O): Data Bus Bit-7_5 GPIO Function: GPIOS[15:12]
V14
BU
U18 U10 P9 U9 T18 V9
BU BU BU BU BU BU
N11
BU
R17,V8
BU
U8
BU
N10
BU
U7, N9, V7
BU
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W99802G
GPIO Pins
PIN NAME PIN NUMBER TYPE DESCRIPTION
GPIO[0] / HGPIO[0] / PCLK-A GPIO[1] / HGPIO[1] / MSRDYO GPIO[2] / HGPIO[2] / FL_TRG GPIO[3] / HGPIO[3] / MSINTO GPIO[5:4] / HGPIO[5:4] / FEINT[1:0] GPIO[7:6] / HGPIO[7:6] / FEINT[3:2] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] USK GPIO[13] / UDI GPIO[14] / UDO GPIO[15] / UCS0 GPIO[16] / UCS1 GPIO[17] / CLK_IN2 GPIO[18] / STDBY GPIO[19] / PCLK-B
V5 A12 P11 P18 P17, U6
BU BU BD BD BU
General Purpose I/O [0] Programmable Clock Output-A (PWM Function) General Purpose I/O [1] Force GPIO[1] to low state. General Purpose I/O [2] Flashlight Trigger Control General Purpose I/O [3] General Purpose I/O [5:4] Fast External Interrupt Input [1:0] General Purpose I/O [7:6] Fast External Interrupt Input [3:2] General Purpose I/O [8] General Purpose I/O [9] General Purpose I/O [10] General Purpose I/O [11] General Purpose I/O [12] Universal Serial Interface (USI): USK General Purpose I/O [13] Universal Serial Interface (USI): UDI General Purpose I/O [14] Universal Serial Interface (USI): UDO General Purpose I/O [15] Universal Serial Interface (USI) : UCS0 General Purpose I/O [16] Universal Serial Interface (USI) : UCS1 General Purpose I/O [17] Clock-2 Input Pin General Purpose I/O [18] System Standby Flag STDBY Output General Purpose I/O [19] / Programmable Clock Output-B (PWM Function)
R18, V6 E18 E2 D1 F18 V3 P7 V4 N8 P10 N17 L17 M17
BD BD BD BD BD BU BU BU BU BU BU BD BD
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
Miscellaneous
PIN NAME PIN NUMBER TYPE DESCRIPTION
XIN XOUT TME RST# S2_PWR Power and Ground
PIN NAME
V13 U13 U14 U17 A3
I O ID IS O
Reference clock input from crystal or clock source. Oscillator output to a crystal. This pin is left unconnected if an external clock source is used. Test Mode Enable. Only for test, this pin must be connected to GND for normal operation. Reset In. This pin is active low to reset chip. Power Plate Control Section 2.
PIN NUMBER
TYPE
DESCRIPTION
VCC VCC_LCM VCC_HIC
F5, F9, M5, N14, P8, B5 C18, E13 B12 F12, F13, F6, F7, G13, G6, K13, M13, M6, N12, N13, N6, N7, V17, B4, A16 B13 E9, P12, P6, E6, A15 V15 U15 A13, A14 V10
P P P
I/O Pad Buffer Power Supply (2.5V~3.3V) I/O Pad Buffer to Frame buffer Power Supply (2.6V~3.3V) HOST BUS Interface Buffer Supply (1.8V~3.3V)
GND
G
Ground.
VDDHI VDDI AVDDP AVSSP FB_VCC VPRO
P P P G P ID
Internal Core Logic Power Supply Internal Core Logic Power Supply PLL Power Supply PLL Ground Frame Buffer Power Supply (2.6V ~ 3.3V) NC
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W99802G
3.2
18 D VRE FC VCC_LCM USB VDD GPIO8 GPIO 11 SVID7 LDAT0 SVID5 SVID9 RI# ADO shs HGPIO3 HGPIO7 GPIOS6 GPIOS2 D RST# GND TMS AVS SP AVD DP TME SD_ CLK XOUT XIN TCK TDI TDO TRST# GPIOS3 VPRO GPIOS5 GPIOS7 SD_ DAT3 SD_ DAT1 GPIOS15 GPIOS13 HGPIO4 HGPIO6 DSR# HGPIO0 RLSD# GPIO 14 GPIO 12 CTS# SOUT2 MSD11 MSD3 MSA2 LRD# LDAT6 LDAT4 SOUT GPIO 18 GPIO 19 GPIO 17 HGPIO5 SD_ DAT2 D MSD15 lCS2# LDAT 13 LDAT9 RTS# SDO SIN VCC D VCC_LCM GND GND LA0 ADO_ DVDD GND SDA GND GND FSCS0# GND VDDI SD_ DAT0 HGPIO 2 SD_ CMD GPIO 16 GPIOS14 GPIOS4 GPIO 15 VCC GND GPIO 13 MSD9 GND MSD1 MSD7 MSRD# MSD5 VDDI VCC msCE# ADI USB VSS GND CDDI GND GND LDAT2 SVID1 SVID2 SVID8 GND GND VDDI D VCC ABC LK LCS 0# LDAT 14 LDAT 12 SCLK VCC DTR# D DM GPI O9 ASC LK LDAT 17 LDAT 15 LDAT 10 LDAT8 LDAT5 LDAT1 SVID4 SPC LK SVS
W99802G Pin Assignment (Bottom View)
17 ADO_ AVDD MIC_ BIAS 16 GND 15 VDD1 ADO_ AVSS 14 FB_ VCC MSA0 13 FB_ VCC VDDHI 12 HGPIO1 VCC_ HIC 11 MSD14 MSD13 10 MSD12 MSD10 9 MSD8 MSD6 8 MSD4 msd16 7 MSD2 MSD0 6 msd17 msa3# 5 mswR# VCC 4 MSA1 GND 3 S2PWR 2 MIC_IN CADI 1 D DP ADO_ DVSS GPIO 10 ARS T# AWS LCS 1# LWR# LDAT 16 LDAT 11 LDAT7 LDAT3 SVID0 SVID3 SVID6 SCK SIN2 D * A B C D E F G H J K L M N P R T U V
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
4. W99802G BLOCK DIAGRAM
Host
GPIO
I-Cache / D-Cache
32-Bit RISC CPU
PLL & Clock Control
Host I/F
Memory Buffer
VPE
Timer INTC UART
USSI
MPEG4 Codec
JPEG Codec
2-D G.E.
USB
Sensor ISP
LCD CTL.
Audio I/F
Memory Card I/F
ADC
USB
Image Sensor
LCDs
MIC
Audio Memory Card Codec Or Melody Chip
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W99802G
5. ELECTRICAL CHARACTERISTICS
5.1 Digital Absolute Maximum Ratings
PARAMETER MIN. MAX. UNIT
Table 5-1 Absolute Maximum Ratings Ambient temperature Storage temperature DC supply voltage for core (1.2V) power (VDDI) DC supply voltage for I/O (3.3V) power (VDDB) I/O pin voltage with respect to VSS -20 -40 0 0 -0.3 85 125 1.3 3.6 VDDB +0.4 C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
5.2
Digital DC Characteristics
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Table 5-2 DC Characteristics
SYMBOL
VDDB AVDDP VDDI VIL VIH VOL VOH IIL IIH IUP IPD IDD Top
Power Supply for I/O Pads Power Supply for PLL Power Supply for Core Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Pull-up Current Power Down Current
No load, Host inactived.
2.6 3.0 1.20 1.20 0 2.0 IOUT = 2mA IOUT = -2mA VIN = 0.4V VIN = 2.4V VIN = 0V 2.4
3.0 3.30 1.25 1.25
3.6 3.6 1.30 1.30 0.8 VDDB +0.3 VSS+0.4 10 -10 -500
V V V V V V V V A A A A mA
USBVDD Power Supply for USB Transceiver
5 VDDB=2.8V VDDI=1.2V -20 15 60
10
Active Current
3GP recording, CIF-30fps
Operation Temperature
70
C
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
5.3
5.3.1
Digital AC Characteristics
Reset AC Characteristics
RST# TRST
Figure 5-1 Reset Timing Diagram
Table 5-3 Reset Timing
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
TRST
Reset Pulse Width
10.0
mS
5.3.2
Clock Input Characteristics
TXIN
XIN THIGH TLOW
1.5 V
FXIN = 1 / TXIN XINDUTY = THIGH / (THIGH + TLOW)
Figure 5-2 Clock Input Timing Diagram
Table 5-4 Clock Input Timing Specification
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
FXIN XINDUTY VIL (XIN) VIH (XIN)
Clock Input Frequency Clock Input Duty Cycle XIN Input Low Voltage XIN Input High Voltage
4 45 0 2.0
12.0 50 55 0.8 VDDB +0.3
MHz % V V
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W99802G
5.3.3 Video Input AC Characteristics
TSPCLK SPCLK THIGH TLOW TSU SVID[7:0] SHS, SVS
input valid
TH
Figure 5-3
Input Video Timing Diagram
Table 5-5 Input Video Timing
SYMBOL PARAMETER MIN. MAX. UNIT
FSPCLK THIGH TLOW TSU TH
SPCLK Frequency = 1 / TSPCLK SPCLK Clock High Time SPCLK Clock Low Time SVID[9:0], SHS, SVS Setup Time SVID[9:0], SHS, SVS Hold Time
--8.0 8.0 1.0 1.0
96 ---------
MHz ns ns ns ns
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W99802G
5.3.4 Host Interface: Memory Bus AC Characteristic
FCE1_,FCE2_ FA2:0]
TCAS TRD TCAH
FIORD#
TODD TODH Valid Data TCAS TWR TCAH
FD[15:0]
FIOWR#
TWDS TW DH
FD[15:0]
Valid Data
Figure 5-4
Host Interface : Memory Bus Timing Diagram
Table 5-6 Host Interface: Memory Bus Timing
SYMBOL PARAMETER MIN. MAX. UNIT
TCAS TCAH TODD TODH TRD TWDS TWDH TWR
Set-up time, FCE1_, FCE2_ and FA valid before FIORD# & FIOWR# low Hold time, FCE1_, FCE2_ and FA valid after FIORD# & FIOWR# high FIORD# Low to Data Valid Delay Read Data Output Hold Time FIORD# Pulse Width Set-up time, FD valid before FIOWR# low Hold time, FD valid after FIOWR# high FIOWR# Pulse Width
0 0 --2.65 12 0 0 12
----8.5 -----------
ns ns ns ns ns ns ns ns
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W99802G
5.3.5 LCD Interface AC Characteristics
LCS_
T LAS T LAH
LA0
TLCSS T LWR TLCSH
80 Mode : LWR#
T LDOD T LDOH Valid Data TLE
LDATA[15:0]
68 Mode : LE
Figure 5-5
LCD Interface Timing Diagram
Table 5-7
SYMBOL
LCD Interface Timing
PARAMETER CONDITIONS MIN. MAX. UNIT
TLCSS TLCSH TLAS TLAH TLDOD TLDOH TLWR TLE
Chip Select Set-up Time Chip Select Hold Time Address Set-up Time Address Hold Time Write Data Active Delay Write Data Hold Time LWR# Pulse Width LE Pulse Width 80 Mode 68 Mode
1/2 1/2 1 1 0 1/2 1/2 1/2
--------1/2 -------
PCLK PCLK PCLK PCLK PCLK PCLK PCLK PCLK
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
5.3.6 SD/MMC Host Interface AC Characteristics
F SD T CLKL SD_CLK T CLKH T OAD SD : CMD, DAT[3:0] MMC : CS, CMD, DAT0 T OH
output valid
SD_CLK T ISU SD : CMD, DAT[3:0] MMC : DAT0
input valid
T IH
Figure 5-6
SD/MMC Host Interface Timing Diagram
Table 5-8
SYMBOL
SD/MMC Host Interface Timing
PARAMETER CONDITIONS MIN. MAX. UNIT
FSD FSD TCLKH TCLKL TISU TIH TOAD TOH
SD/MMC Clock Frequency SD/MMC Clock Frequency SD/MMC Clock High Time SD/MMC Clock Low Time CMD & Data Input Setup Time CMD & Data Input Hold Time Output Active Delay (Falling Edge) Output Hold Time
Identification Mode Data Transfer Mode
0 0 10 10 5 5 --20
400 25 --------14 ---
KHz MHz ns ns ns ns ns ns
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W99802G
5.3.7 NAND Flash Memory Interface AC Characteristics
SCS#, S AL E, SCL E
T C ACS TW P
TW C TW H T C ACH
SW E#
T W DS T W DH
SD[7:0]
W AD-0
W AD-1
W AD-2
T RC T C ACS T RP T RH T C ACH
SRE#
T RDS T RDH
SD[7:0]
RD-0
RD-1
RD-2
Figure 5-7 NAND Flash Memory Interface Timing Diagram
Table 5-9
SYMBOL
NAND Flash Memory Interface Timing
PARAMETER MIN. MAX. UNIT
TCACS TCACH TWP TWH TWC TWDS TWDH TRP TRH TRC TRDS TRDH
SCS#, SALE, SCLE Setup Time before SWE#, SRE# Low SCS#, SALE, SCLE Hold Time after SWE#, SRE# High Write Pulse Width SWE# High Time Write Cycle Time Write Data Ouptut Setup Time Write Data Output Hold Time Read Pulse Width SRE# High Time Read Cycle Time Read Data Input Setup Time Read Data Input Hold Time
20 40 40 20 80 30 20 40 20 80 30 20
-------------------------
ns ns ns ns ns ns ns ns ns ns ns ns
- 23 -
Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
5.3.8 Audio I2S Interface AC Characteristics
TABCLK TABCLKH TABCLKL
ABCLK
TAOS TAOH
AWS, ADO
ABCLK
TAIS TAIH
ADI
Figure 5-8
Audio I2S Interface Timing Diagram
Table 5-10
SYMBOL
Audio I2S Interface Timing
PARAMETER MIN. MAX. UNIT
TABCLKH TABCLKH TABCLK TAOS TAOH TAIS TAIH
Audio Bit Clock Output
High Time
16 16 40 8 8 8 8
---------------
ns ns ns ns ns ns ns
Audio Bit Clock Output Low Time Audio Bit Clock Output Cycle Time Audio Data Output Setup Time Audio Data Output Hold Time Audio Data Input Setup Time Audio Data Input Hold Time
- 24 -
W99802G
5.3.9 Host Universal Synchronous Serial Interface AC Characteristics
TUCK TUCKL UCK TUCKH TUOS UCS, UDO TUOH
output valid
UCK TIUIS UDI
input valid
TIUIH
Figure 5-9 Universal Synchronous Serial Interface Timing Diagram
Table 5-11
SYMBOL
Host Universal Synchronous Serial Interface Timing
PARAMETER MIN. MAX. UNIT
TCLKH TCLKL TCLK TUOS TUOH TUIS TUIH
Clock Output High Time Clock Output Low Time Clock Cycle Time UCS#, UDO Output Setup Time UCS#, UDO Output Hold Time UDI Input Setup Time UDI Input Hold Time
0.4 0.4 1.0 0.3 0.3 0.3 0.3
---------------
SCLK SCLK SCLK SCLK SCLK SCLK SCLK
Note: SCLK = 4 * PCLK (APB Clock, the frequency of this clock is specified by Clock Divider Register-0 & 1)
- 25 -
Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
5.3.10 USB Transceiver AC Characteristics
Rise Time CL Differential Data Lines 90% 10% 90%
Fall Time
10%
CL Full Speed: 4 to 20ns at CL = 50pF
tR
tF
Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF
Figure 5-10
Data Signal Rise and Fall Time
TPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2
Figure 5-11
Differential Data Jitter
TPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data to SE0 Skew N * TPERIOD + TDEOP
Source EOP Width:
TEOPT
Receiver EOP Width: TEOPR1, TEOPR2
Figure 5-12
Differential to EOP Transition Skew and EOP Width
- 26 -
W99802G
TPERIOD Differential Data Lines
TJR Consecutive Transitions N * TPERIOD + TJR1 Paired Transitions N * TPERIOD + T JR2 T JR1 T JR2
Figure 5-13
Receiver Jitter Tolerance
Table 5-12
SYMBOL
USB Transceiver AC Characteristics
PARAMETER CONDITIONS MIN. MAX. UNIT
TR TF TRFM TDRATE
Rise Time Fall Time Rise/Fall Time Matching Full Speed Data Rate Source Differential Driver Jitter
CL = 50 pF CL = 50 pF Average bit rate (12 Mb/s 0.25%)
4 4 90 11.97
20 20 110 12.03
ns ns % Mbps
TDJ1 TDJ2 TEOPT TDEOP TJR1 TJR2 TEOPR1 TEOPR2
To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver Data Jitter Tolerance To Next Transition For Paired Transitions EOP Width at Receiver Must Reject as EOP Must Accept as EOP
-3.5 -4.0 160 -2 -18.5 -9 40 82
3.5 4.0 175 5 18.5 9
ns ns ns ns ns ns ns ns
- 27 -
Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
5.4
5.4.1
Audio Interface (ADC) Characteristics
Recommend Operation Conditions
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Digital Supply Range Analog Supply Range Ground Temperature
ADO_DVDD AVDD DVSS, AVSS TA
1.1 2.5 -20
1.2 3.0 0
1.3 3.6 85
V V V
o
C
5.4.2
Electrical Characteristics
o
Conditions: DVDD = 1.2V, AVDD = 2.7V, TA = 30 C, 1KHz Signal, fs = 48 KHz, 16-bit audio data.
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
ADC : Analog Input (MIC_IN) Full Scale Input Signal Level (for ADC 0dB Input at 0dB Gain) Input Resistance Input Capacitance Signal to Noise Ratio Dynamic Range Total Harmonic Distortion Analog Reference Level Reference Voltage Microphone Bias Bias Voltage Bias Current Source VMICBIAS IMICBIAS 3mA load current -5% 0.9* AVDD +5% 3 V mA VREFC -3% 1.2 +3% V THD SNR 90 VINFS AVDD = 2.5V 11.2 10 70 95 70 0.707 44.8 Vrms Kohm. pf dB dB dB
- 28 -
W99802G
6. PACKAGE DIMENSION
W99802G Package Outline (184L STK LFBGA)
A1 CORNER
1 A 2 3 4 5 6 7
TOP VIEW
8 9 10 11 12 13 14 15 16 17 18
0.27~0.37(184X)
18 17 16 15 14 13
BOTTOM VIEW
12 11 10 9 8 7 6 5 4 3
A1 CORNER
2 1
A
0.5
+ 0.15
8.50
10.00
B B C C D E E F F G G H H D
W99802G
J K L M N P R T U
J K L M N P R T U
0.20 C
V
0.86Ref.
V
0.08 C
A B
0.15(4X)
0.5 8.50 10.00 + 0.15
0.26Ref.
Package Type : 184L STK LFBGA PACKAGE SIZE : 10.00x10.00x1.60MM UNIT : MM Ball Pitch : 0.50 Ball Diameter : 0.3 Substrate Thickness : 0.26 Mold Thickness : 0.86
1.60 Max.
C
0.16 ~ 0.26
SEATING PLANE
0.08 M 0.15 M
C CA B
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Publication Release Date: Mar. 3, 2006 Revision A0
W99802G
7. W99802G APPLICATION DIAGRAM
Sensor Module
Memory Buffe r Sensor DSP JPEG 2D GE FMI VCE VPOST MPEG4 VPE USB
LCM1 LCM2
Audio
Base Band
HIC
ARM CPU
Melody
MIC
APB
High Speed UART USSI GPIO PWM
NAND
- 30 -
W99802G
8. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A0
Mar. 3, 2006
Public Edition
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. USE OF THIS PRODUCT W99802G IN ANY MANNER THAT COMPLIES WITH ANY OF THE MP3, WMA, MPEG4, 3GP, AAC, AND/OR ANY OTHER TECHNOLOGY STANDARDS IS EXPRESSLY PROHIBITED WITHOUT A LICENSE UNDER APPLICABLE PATENTS IN EACH OF THE MP3, WMA, MPEG4, 3GP, AAC, AND/OR ANY OTHER TECHNOLOGY STANDARDS PATENT PORTFOLIO, WHICH LICENSE IS AVAIBLE FROM RESPECTIVE COMPETENT AUTHORITY LICENSOR." "NEITHER SHALL WINBOND BE LIABLE FOR ANY LICENSE FEE, ROYALTY, AND/OR ANY OTHER EXPENSE OR COST ACCRUED FROM THE SAID LICENSE(S), NOR SHALL WINBOND BE RESPONSIBLE FOR INFRINGEMENT OF THE RIGHT OF PATENT CAUSED OUT OF THE INAPPROPRIATE USE OF THIS PRODUCT BY CUSTOMER.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 31 -
Publication Release Date: Mar. 3, 2006 Revision A0

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